Tag: Cadence JasperGold

Shift left – a path to faster and better SOC quality A revolution is happening in the chip design industry. A revolution that allows projects to finish earlier, with fewer bugs, while budget stays in control. In this article, I’ll share my personal view on a few related bottlenecks that directly affect time to market […]

Introduction As the size and complexity of modern integrated circuits grow, semiconductor development teams are challenged to provide verification coverage for these larger, more complex chips with the same tight schedules. Formal Verification is an Electronic Design Automation (EDA) application commonly used by development teams to achieve this end. However, verification of modern Systems-on-Chip (SoC) designs increases […]