Tag: semiconductor verification

Using advanced node technology to successfully manufacture a chip is getting harder as chip geometries continue to shrink. Electronic Design Automation (EDA) consumes more compute, storage, and time. Giving your engineers more time to iterate and find bugs in the design and verification phases will result in saving millions in re-spins and lost revenue. Further […]

58th Annual Design Automation Conference The 58th annual Design Automation Conference took place in San Francisco from December 5 – 9, 2021. The Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits. DAC focuses on the latest methodologies and technology advancements in electronic design. […]

Design and Verification Conference 2021 (DVCon) The Design and Verification Conference (DVCon) is the leading event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative™, DVCon brings chip architects, design and verification engineers, and IP integrators the latest methodologies, […]

Introduction As the size and complexity of modern integrated circuits grow, semiconductor development teams are challenged to provide verification coverage for these larger, more complex chips with the same tight schedules. Formal Verification is an Electronic Design Automation (EDA) application commonly used by development teams to achieve this end. However, verification of modern Systems-on-Chip (SoC) designs increases […]