Rigetti Computing builds and deploys integrated quantum computing systems leveraging superconducting qubit technology. These systems enable organizations to augment existing computational workflows with quantum processors. Rigetti serves customers in finance, insurance, pharmaceuticals, defense, and energy with custom software and full-stack solutions focused on simulation, optimization, and machine learning applications. The company is headquartered in California, with offices in Washington, DC, Australia, and the UK.

“Providing AWS customers access to Rigetti QPUs is an important part of accelerating the commercialization of quantum computing. Our AWS collaboration enables end users to develop quantum algorithms using our state-of-the-art quantum hardware, enabling a wide range of application and research progress that will guide the industry forward.”

Dr. Subodh Kulkarni, CEO of Rigetti Computing

Superconducting Quantum Processors

Rigetti Superconducting Quantum Processors

Rigetti quantum processors are universal, gate-model machines based on superconducting qubits. Universal, gate-based quantum computers can have applications in areas including chemical simulation, combinatorial optimization, and machine learning. Because coherent superconducting qubits operate on the same quantum mechanical principles that govern nature, they can be used to efficiently simulate and understand the behavior of biochemical mechanisms, for example photosynthesis and protein folding. In addition, quantum computers can be used to navigate exponentially more state space to find more optimal solutions among an incalculable set of possibilities, for example in global logistics management.

The Rigetti Aspen-series chips feature tileable lattices of alternating, fixed-frequency and tunable superconducting qubits within a system architecture that is scalable to large qubit counts. Parametric entangling logic gates on these chips also offer fast gate times and program execution rates. Performance metrics for current Rigetti systems, including gate fidelities and coherence times, can be found on Rigetti's QPU page.

Rigetti processors consist of three principal subsystems. First, user programs are optimized into machine-native instructions through a compiler tool chain. Then, a low-latency hardware controller sequences these instructions as calibrated electrical signals. Finally, the qubits, made from coherent superconducting circuit elements, transduce these electrical signals logically as digital quantum gates and measurement instructions. 

Figure 1 - Rigetti Aspen-M chip architecture

About Rigetti's Quantum Chips

Rigetti’s Aspen processor features enhanced readout capabilities that contribute to better overall circuit fidelities. Further system improvements and device characteristics include a speedup in quantum processing times, fast gate times for multiple entangling gate families, and rapid sampling via active register reset.

The Aspen chip topology is octagonal with 3-fold (2-fold for edges) connectivity and features both CPHASE and XY entangling gates that allow developers to optimize programs for performance and minimize circuit depth. SWAP gates shuttle quantum information across the Aspen processor to link non-nearest neighbor qubits. Because these can be costly operations, the underlying compiler is highly optimized for the “layout problem.”

Amazon Braket currently offers access to two different QPUs from Rigetti Computing. Rigetti's Aspen-M processor is based on scalable multi-chip technology and is assembled from two 40-qubit chips. 

The processor topology is shown in Fig 1, and includes direct couplings between a single qubit and its three nearest neighbors.

Rigetti’s two-qubit entangling gate mechanism (typically a controlled-phase gate or “CPHASE” gate) is actuated by electrical frequency modulation (FM) control. For these “parametric gates” to execute this instruction, the radio dial of one qubit is flipped into resonance with a nearest-neighbor qubit for a precisely defined duration. On the Aspen graph, this scheme requires that at least half of the qubits are FM-tunable. The integrated circuit is designed to minimize cross-talk between the qubits. To estimate the effect of decoherence on an algorithm, the lifetimes of the qubits (~20 μs) should be compared to the gate duration (~40-180 ns) multiplied by the circuit depth of the algorithm.