Boson

Partcls flagship product, Boson, is an accelerated EDA platform for full RTL to GDSII design. Boson is developed on GPUs to enable up to 1000x speed improvements over legacy tools without compromising accuracy. Boson accepts standard design collateral including RTL, DEF files, Liberty files, PDK information from standard foundries, and generates standard output files for interoperability with existing EDA tools. Modern chip design cycles are bottlenecked by lengthy physical design processes, limited compute resources, and manual optimization loops. These challenges can cost engineering teams weeks of effort and delay product delivery for semiconductor companies. Partcls cloud-native, GPU-accelerated EDA suite, featuring Boson, RTL Super Optimization, and Nucleus, enables rapid physical design feedback and automated design space exploration. The platform combines AI, GPU parallelism, and modern serverless infrastructure to improve timing closure, optimize power, performance, and area (PPA), and accelerate silicon design iterations. Key Features RTL Super Optimization

AI-driven design space exploration that automatically improves RTL-level power, performance, and area. Boson Physical Design Toolchain

End-to-end GPU-accelerated synthesis, placement, clock tree synthesis (CTS), buffer insertion, and timing analysis. Nucleus Database

High-performance physical design database and parsers purpose-built for GPU workflows. Rapid PPA Feedback

Real-time power, performance, and area estimation within seconds. Serverless Deployment

Cloud-based scalability using Modal serverless endpoints for each EDA operation. CLI and API Access

Command-line tools and APIs for seamless integration into CI/CD and hybrid design environments. Benefits Reduce design iteration time from weeks to hours. Achieve up to 10x faster timing closure compared to traditional EDA flows. Optimize designs earlier in the development cycle, reducing compute and engineering costs. Improve power, performance, and area through AI-guided optimization. Enable real-time, interactive EDA workflows with GPU acceleration. Target Audience and Use Cases Semiconductor design teams developing SoCs, ASICs, or AI accelerators. Academic researchers and chip startups seeking high-performance, cost-efficient EDA workflows. Engineering teams targeting advanced process nodes, including 4nm and below, that require rapid design feedback and accelerated design iteration.