The simulation cannot work
Cannot see the waveform using Vivado. Try to find solution on forum, but it seems no good solution for this problem.
Specify scope of logic for wave dump The file $AWS_FPGA_REPO_DIR/hdk/cl/examples/cl_dram_dma/verif/scripts/waves.tcl specifies the scope of logic for wave dump. The default behavior is to dump only the signals at the very top of the design: add_wave / To recursively dump waves of all signal underneath the top level of the design, add -recursive: add_wave -recursive / Note that dumping all signals of a design will increase simulation time and will result in a large file.
Did you use RDP to connect to the instance? Then you should be able to use the GUI and see the waveforms.