Tag: EDA

Single cell RNA sequencing data has a growing role in disease research for finding both potential genetic factors and paths to new treatments. An important component of this process involves building maps of sequencing data with dimensionality reduction tools and querying specific subsets for visualization, but this can be slow due to the size of […]

Introduction The Semiconductor Industry is working to establish Environmental, Social, and Corporate Governance (ESG) standards with the help of science-based targets. According to the Science Based Targets (SBT) Initiative (SBTi), “SBTs provide a clearly defined pathway for companies to reduce greenhouse gas (GHG) emissions, helping prevent the worst impacts of climate change and future-proof business […]

Introduction Electronic Design Automation (EDA) workloads have traditionally run on-premises on a combination of latest and older generation compute servers. The performance penalty of running Electronic Design Automation (EDA) on older generation hardware is often neglected in discussions and Total Cost of Ownership (TCO) models. With EDA license costs greatly exceeding IT spend in silicon […]

Shift left – a path to faster and better SOC quality A revolution is happening in the chip design industry. A revolution that allows projects to finish earlier, with fewer bugs, while budget stays in control. In this article, I’ll share my personal view on a few related bottlenecks that directly affect time to market […]

Introduction Silicon designers are creating increasingly complex designs to address ever-increasing demand from customers. Increased complexity poses challenges to electronic design automation (EDA) applications that help with manufacturability and functionality of the designs on silicon. Physical verification is an integral part of the silicon design system that identifies design layout issues prior to its production […]

Introduction Designing semiconductor requires High Performance Computing (HPC) to run Electronic Design Automation (EDA) tools. These workloads vary over time in both the amount and type of compute resources required. This makes it an ideal workload for the elasticity of the cloud. Customers choose optimal instance types to optimize each tools runtime. This reduces time-to-results […]

University faculty members and non-profit organizations looking to improve the training experience for the next generation of microelectronics engineers face multiple challenges with the computing environment required, both technical and organizational. In this blog we will review these challenges, and how to solve them using ready-made solutions on AWS and how these solutions can scale […]

Introduction Chip designs are increasing in complexity and size, which has resulted in additional transistors driving a need for greater processing power and memory. Greater silicon complexity makes physical verification with electronic design automation (EDA) applications more essential as any delays close to tape-out significantly impact production timelines. Silicon designers now require increased CPU and […]

Introduction Chip design is not only compute and memory intensive, it also requires varying amounts of resource in different Integrated Circuit (IC) design phases: some frontend tools are single threaded and CPU bound, while backend tools rely on high performance storage and large memory. Fixed-size compute farms on-premises result in jobs waiting in queue for […]

Introduction This post will walk you through the configuration of this powerful EDA solution and provide performance benchmarks. Semiconductor design simulation, verification, lithography, metrology, yield analysis, and many other workloads benefit from the scalability and performance of the AWS Cloud. For example, the by latest generation EC2 instance types enhance compute performance for these applications. […]